Doctorates' Information System

     Ayan Palchaudhuri

Ph.D. fromIndian Institute of Technology Kharagpur - Electronics and Electrical Communication Engineering
Supervisor(s)  Dr. Anindya Sundar Dhar
Ph.D. status  Joined in 2014 :: In progress
AddressRoom No. D408, Dr B.R.Ambedkar Hall, IIT Kharagpur, Pin 721302
Phone----
Emailayanpalchaudhuri@gmail.com
Formal Education
Exam / Degree Board / UnivBranchYear
M.Tech.Indian Institute of Technology KharagpurComputer Science and Engineering2015
B.Tech.The West Bengal University of TechnologyElectronics and Communication Engineering2010
12Council for the Indian School Certificate ExaminationsScience2006
10Council for the Indian School Certificate ExaminationsScience2004

Research Areas
  • VLSI Architecture Design
  • Computer Arithmetic

Skills
  • Verilog, VHDL, MATLAB, C

Awards
  • Best Poster Award in the Student Research Symposium of the 21st IEEE International Conference on High Performance Computing (HiPC) 2014

Experience
  • Junior Project Assistant in the project titled- Hardware Security, Ensuring TRUST in Integrated Circuits, at IIT Kharagpur in the Dept. of CSE from Feb 2011 to Oct 2013

Teaching Experience
  • Architectural Design of ICs(T) at Dept. of EECE, IIT Kharagpur 1 Semester (1 terms)
  • VLSI for Telecommunication(T) at Dept. of EECE, IIT Kharagpur 1 Semester (2 terms)
  • Refresher Course on Digital Signal Processing From Theory to Practice(L) at Dept. of EECE, IIT Kharagpur 1 semester (1 terms)
  • Linear Algebra and Error Control Techniques(T) at Dept. of EECE, IIT Kharagpur 1 Semester (1 terms)
  • VLSI Laboratory(P) at Dept. of EECE, IIT Kharagpur 1 semester (1 terms)
  • Introduction to Electronics Laboratory(P) at Dept. of EECE, IIT Kharagpur 1 semester (1 terms)
  • Basic Electronics Theory(T) at Dept. of EECE, IIT Kharagpur 1 semester (1 terms)
  • Basic Electronics Laboratory(P) at IIT Kharagpur 1 semester (1 terms)
  • Image Processing(T) at Dept. of CSE, IIT Kharagpur 1 Semester (1 terms)
  • High Performance Computer Architecture(T) at Dept. of CSE, IIT Kharagpur 1 Semester (1 terms)
  • Discrete Structures(T) at Dept. of CSE, IIT Kharagpur 1 Semester (1 terms)
  • Switching Circuits and Logic Design(T) at Dept. of CSE, IIT Kharagpur 1 Semester (1 terms)
  • Switching Circuits and Logic Design Laboratory(P) at Dept. of CSE, IIT Kharagpur 1 Semester (1 terms)
  • Introduction to Verilog(L) at Dept. of CSE, IIT Kharagpur Short Term Course- FPGA Prototyping Using Verilog (1 terms)
  • Digital Design Flow for Xilinx FPGAs and FPGA Architectures(L) at IIT Kharagpur Summer Course in the Advanced VLSI Design Lab. (1 terms)
  • VLSI System Design(L) at Dept. of CSE, IIT Kharagpur 2 semesters (2 terms)
  • Short Term Course on Advances in VLSI Signal Processing(L) at Dept. of EECE, IIT Kharagpur 5 days (2 terms)
  • Short Term Course on Advanced DSP Design Techniques(L) at Dept. of EECE, IIT Kharagpur 5 days (4 terms)

Fellowships / Scholarships
  • MHRD Fellowship for pursuing PhD at IIT Kharagpur
  • Student Fellowship at the 20th International Symposium on VLSI Design and Test (VDAT) 2017
  • Student Fellowship at the 20th International Symposium on VLSI Design and Test (VDAT) 2016
  • Student Fellowship at the 28th International Conference on VLSI Design, 2015
  • Student Fellowship at the21st IEEE International Conference on High Performance Computing (HiPC) 2014
  • Assistantship for working as Junior Project Assistant in the Dept. of CSE, IIT KGP, from Feb. 2011- Sep. 2013
  • Student Fellowship at the 16th International Symposium on VLSI Design and Test, 2012

Papers Published in Journals
  • Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations by A. Palchaudhuri, A. S. Dhar Journal of Electronic Testing 33, 529-537 (2017)
  • Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs by A. Palchaudhuri, A. A. Amresh, A. S. Dhar Journal of Cellular Automata 12, 217-247 (2017)
  • High Performance Integer Arithmetic Circuit Design on FPGA- Architecture, Implementation and Design Automation by A. Palchaudhuri and R. S. Chakraborty Springer, ISBN 9788132225195 (print), 9788132225201 (ebook) Book (2016)
  • A Fabric Component based Approach to the Architecture and Design Automation of High Performance Integer Arithmetic Circuits on FPGA by A. Palchaudhuri and R. S. Chakraborty Computational Intelligence in Electronic Design - Digital and Network Designs and Applications, Springer, Switzerland, ISBN 978-3-319-20070-5 (print), 978-3-319-20071-2 (ebook) Book Chapter (2015)
  • Architecture and Design Automation of High Performance Large Adders and Counters on FPGA through Constrained Placement by R.S. Chakraborty and A. Palchaudhuri International PCT application filed in April 2014, Ref- PCT/IB2014/060372, Indian Patent filed in February 2014, Ref- 179/KOL/2014 Patent (2014)
  • Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream by R. S. Chakraborty, I. Saha, A. Palchaudhuri and G. K. Naik IEEE Design and Test of Computers 30, 45-54 (2013)

Papers Presented at Conferences
  • High Performance Bit-Sliced Pipelined Comparator Tree for FPGAs by A. Palchaudhuri and A. S. Dhar 20th International Symposium on VLSI Design and Test (VDAT) 1-6 (2016)
  • Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs by A.Palchaudhuri and A.S.Dhar 29th International Conference on VLSI Design 433-438 (2016)
  • Automated Design of High Performance Integer Arithmetic Cores on FPGA by A. Palchaudhuri, R.S. Chakraborty, D.P. Sahoo 18th Euromicro Conference on Digital System Design (DSD) 322-329 (2015)
  • Architecture and Design Automation of High Performance Arithmetic Architectures on FPGAs by A. Palchaudhuri and R. S. Chakraborty User/Designer Track of the 28th International Conference on VLSI Design  (2015)
  • High Performance Integer Arithmetic Circuit Design on Reconfigurable Computing Platforms by A. Palchaudhuri and R. S. Chakraborty Student Research Symposium of the 21st IEEE International Conference on High Performance Computing (HiPC) (Poster) (2014)
  • Highly Compact Automated Implementation of Linear CA on FPGAs by A. Palchaudhuri, R. S. Chakraborty, Md. Salman, S. Kardas and D. Mukhopadhyay 11th International Conference on Cellular Automata for Research and Industry (ACRI) 8751, 388-397 (2014)
  • Effect of Malicious Hardware Logic on Circuit Reliability by S. Burman, A. Palchaudhuri, R. S. Chakraborty, D. Mukhopadhyay and P. Singh 16th International Symposium on VLSI Design and Test (VDAT) 7373, 190-197 (2012)

Indian Institute of Technology, Kharagpur-721 302, INDIA
Telephone Number +91-3222-255221 | FAX : +91-3222-255303