Doctorates' Information System

     Atin Mukherjee

Ph.D. fromIIT Kharagpur - Electronics and Electrical Comm Engg.
Supervisor(s)  A. S. Dhar
Ph.D. status  Joined in 2011 :: In progress
AddressVS Hall
Phone9432892150
Emailmukherjeeatin@gmail.com
Formal Education
Exam / Degree Board / UnivBranchYear
M.Tech.IIT KharagpurElectronics and Electrical Communication Engg2011
BEJadavpur UniversityElectronics and Telecommunication Engg2009
12Narendrapur Ramakrishna MissionScience2005
10WBBSEgeneral2003

Research Areas
  • Fault Tolerant VLSI Architecture Design
  • Multimedia and Signal Processing

Teaching Experience
  • Digital Circuits(T) at IIT KGP one semester (1 terms)
  • Introduction to Electronics(T) at IIT KGP one semester (1 terms)
  • Analog Circuits Design(T) at IIT KGP one semester (2 terms)
  • Basic Electronics Lab(P) at IIT KGP one semester (3 terms)
  • Architectural Design of ICs(T) at IIT KGP one semester (1 terms)
  • Digital Circuits Lab(P) at IIT KGP one semester (3 terms)
  • Analog Circuits Lab(P) at IIT KGP one semester (2 terms)
  • Digital VLSI Circuits(T) at IIT KGP one semester (1 terms)

Papers Presented at Conferences
  • New QL-QT Static Redundancy Method for Fault Tolerant Architecture Design by Atin Mukherjee, Anindya Sundar Dhar International Conference on VLSI and Signal Processing (ICVSP) accepted (2014)
  • Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture by A. Mukherjee, A. S. Dhar Electronic System Design (ISED) 2012 IEEE Conference ISED 2012, pp. 92-96 (2012)
  • Design of a Fault-Tolerant Conditional Sum Adder by A. Mukherjee, A. S. Dhar Progress in VLSI Design and Test 2012 Springer LNCS 7373, pp. 217-222 (2012)
  • Double-Fault Tolerant Architecture Design for Digital Adder by A. Mukherjee, A. S. Dhar IEEE Students Technology Symposium (TechSym), 2014 IEEE Techsym 2014, pp. 154-158 (2014)

Indian Institute of Technology, Kharagpur-721 302, INDIA
Telephone Number +91-3222-255221 | FAX : +91-3222-255303