Doctorates' Information System

     Soumya J

Ph.D. fromIIT Kharagpur - Electronics and Electrical Communication Engineering
Supervisor(s)  Prof. Santanu Chattopdhyay
Ph.D. status  Joined in 2010 :: Completed in 2015
AddressMicroprocessor Lab, Department of E and ECE, IIT Kharagpur
Phone03222281482
Emailsoumyaj@ece.iitkgp.ernet.in
Formal Education
Exam / Degree Board / UnivBranchYear
10Board of Secondary Education, Andhra Pradesh-2001
12Board of Intermediate Education, Andhra PradeshMPC2003
B.Tech.JNTU, HyderabadECE2007
M.Tech.Indian Institute of Technology, KharagpurEmbedded Systems2010

Research Areas
  • Application Specific Network on Chip Synthesis
  • Reconfigurable Network on Chip Design

Experience
  • ISRO, Bangalore from 14/09/2011 to 15/06/2012
  • Faculty, NIT Goa from 30/12/2014 to 15/05/2015
  • Faculty, BITS Pilani, Hyderabad Campus from 29/06/2015 till date

Teaching Experience
  • Embedded Systems Design(T) at IIT Kharagpur Autumn 2009 (1 terms)
  • Embedded Systems Lab(P) at IIT Kharagpur Autumn 2009 (1 terms)
  • Design and Analysis of Algorithms(T) at IIT Kharagpur Spring 2010-2012 (2 terms)
  • Basic Electronics Lab(P) at IIT Kharagpur Spring 2013 (1 terms)
  • Basic Electronics(T) at IIT Kharagpur Autumn 2013 (1 terms)
  • Embedded Systems Lab(P) at IIT Kharagpur Autumn 2013 (1 terms)

Papers Published in Journals
  • Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router by Santanu Kundu, Soumya J., Santanu Chattopadhyay Microprocessors and Microsystems - Embedded Hardware Design 36(6),471-488 (2012)
  • Application Specific Network-on-Chip Synthesis with flexible router placement by Soumya J, Santanu Chattopadhyay Journal of Systems Architecture 59, 361-371 (2013)
  • Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration by Soumya J., Ashish Sharma, Santanu Chattopadhyay ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, 2, Article 7 (2014)
  • Area-Performance Trade-off in Floorplan Generation of Application-Specific Network-on-Chip with Soft Cores by Soumya J., Srijan Tiwary, Santanu Chattopadhyay Journal of Systems Architecture 61, 1, 1-11 (2015)
  • Integrated Core Selection and Mapping for Mesh based Network-on-Chip Design with Irregular Core Sizes by Soumya J, K. Naveen Kumar, Santanu Chattopadhyay Journal of Systems Architecture Accepted (2015)

Papers Presented at Conferences
  • Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis by Soumya J., Putta Venkatesh, Santanu Chattopadhyay ISVLSI 2011 341-342 (2011)
  • A Locally Reconfigurable Network-on-Chip Architecture and Application Mappingonto it by Soumya J., Ashish Sharma, Santanu Chattopadhyay VDAT 1-6 (2014)
  • A Constructive Heuristic for Application Mapping onto an Express Channel based Network-on-Chip by Sandeep Dsouza, Soumya J, Santanu Chattopadhyay VDAT Accepted (2015)

Indian Institute of Technology, Kharagpur-721 302, INDIA
Telephone Number +91-3222-255221 | FAX : +91-3222-255303