Doctorates' Information System

     Manas Kumar Hati

Ph.D. fromIIT Kharagpur, ATDC - working in AVLSI Laboratory
Supervisor(s)  Prof. Tarun Kanti Bhattacharyya(Dept E and ECE)
Ph.D. status  Joined in 2010 :: Completed in 2016
AddressBidhan Chandra Roy Hall, IIT Kharagpur, W-107
Phone9748582612
Emailmanasrpef@gmail.com
Formal Education
Exam / Degree Board / UnivBranchYear
12West BengalScience2001
B.Sc.University of Calcutta/Ramakrishna Mission(BelurMath)Physics Hons.2004
B.Tech.Institute of Radio-physics and Electronics, University of CalcuttaRadio-Physics and Electronics(ECE)2007
M.Tech.Institute of Radio-physics and Electronics, University of CalcuttaRadio-Physics and Electronics(ECE)2009

Research Areas
  • Analog/Mixed-Signal/RF IC design
  • Delta Sigma fractional-N PLL frequency synthesizers
  • ADC/DAC/DEM-DAC/Delta Sigma ADC
  • DVB-H Tuner IC Design
  • VLSI System Design
  • VLSI System Design using Verilog HDL

Skills
  • Analog and Mixed signal circuits design with Layout in Cadence environment, I/O ring formation
  • Matlab, Coventor ware for MEMS design
  • Programming Language C, C-plus plus, Java

Awards
  • Kanodia Research Award
  • Bimalendu Ghosh Memorial Medal.
  • Best paper award in IEEE conference ICCPCT 2014
  • Microelectronics Journal, Volume 44, Issue 8, 2013, Pages 649-657, article is now featured online on Advances In Engineering, Also shared in Engineering community.
  • Achievements- He has solved a few open problems
  • WB-JEE, 2001
  • JAM-for IIT Master degree, 2004

Experience
  • Primatelicom Limited, ENG. R and D, NOIDA, Taiwan
  • Reviewer-IEEE TCAS-1, IEEE Transaction VLSI, MIcroelectronics Journal, Integration on VLSi, IETE Taylor and Francis
  • Project Officer at IIT Madras, EE Dept., Sept.-to - Dec. 2016

Teaching Experience
  • Communications, Computer Science, VLSI (Digital and Analog)(L) at Institute of Technology and Marine Engineering, WBUT Six months (1 terms)
  • Advanced VLSI Lab., Summer course instructor for the year of 2012, 2013(L) at IIT Kharagpur Two Months (2 terms)
  • VLSI System Design and implementation using Verilog HDL(L) at NIT Durgapur one semester (1 terms)

Fellowships / Scholarships
  • FFE(Foundation for Excellence, INDIA, USA)2001-2007
  • MHRD, Institute scholarship, 2010-2014
  • GATE (ECE) 2008, 2015.

Papers Published in Journals
  • A High O/P Resistance, Wide Swing and Perfect Current Matching Charge Pump having Switching Circuit for PLL by Manas Kumar Hati and Tarun K. Bhattacharyya Microelectronics Journal 44, 649-657 (2013)
  • Methods of loop bandwidth calibration and phase noise cancellation circuits in a fractional N PLL with a special switching charge pump circuit to reduce the leakage current, o/p noise and spur by Manas Kumar Hati and Tarun K. Bhattacharyya Indian Patent, Ref 0957/KOL/2013 1-30 (2013)
  • A novel high speed pulse swallow based fractional-N frequency divider circuit by Manas Kumar Hati and Tarun K. Bhattacharyya Indian Patent Filed (Ref- 0680/KOL/2014) 1-30 (2014)
  • Auto Calibrated Delta-Sigma Fractional-N PLL Frequency Synthesizers with Loop Bandwidth Calibration and Phase Noise Cancellation using PFD/DAC based Unit Current Cell by Manas Kumar Hati and Tarun K. Bhattacharyya Indian Patent Filed (Ref-1004/KOL/2015) 1-46 (2016)
  • A Fast Automatic Frequency and Amplitude Control LC-VCO Circuit with Noise Filtering Technique for a Fractional-N PLL Frequency Synthesizer by Manas Kumar Hati and Tarun K. Bhattacharyya Microelectronics Journal, Elsevier- 2016 52, 134-146 (2016)
  • A Fast and Efficient Constant Loop Bandwidth with Proposed PFD and Pulse Swallow Divider Circuit in Delta Sigma Fractional-N PLL Frequency Synthesizer by Manas Kumar Hati and Tarun K Bhattacharyya Microelectronics Journal 61, 21-34 (2017)
  • Auto Calibrated Delta Sigma Fractional-N PLL Frequency Synthesizer with Loop Bandwidth Calibration and Phase Noise Cancellation by Manas Kumar Hati and Tarun K Bhattacharyya Communicated 1-13 (2016)

Papers Presented at Conferences
  • A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC by Manas Kumar Hati and Tarun K. Bhattacharyya 25th International Conference on VLSI Design held jointly with 11th International Conference on Embedded Systems Design, 2012 45-50 (2012)
  • A Power Efficient and Constant-gm 1.8 V CMOS Operational Transconductance Amplifier with Rail-to-Rail Input and Output Ranges for Charge Pump in Phase-Locked Loop by Manas Kumar Hati and Tarun K. Bhattacharyya International Conference on Devices, Circuits and Systems, ICDCS-2012. 38-43 (2012)
  • A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL by Manas Kumar Hati and Tarun K. Bhattacharyya Proceedings of the 16th international conference on Progress in VLSI Design and Test 166-171 (2012)
  • Dgital video broadcast services to handheld devices and a simplified DVB-H receiver subsystem by Manas Kumar Hati and Tarun K. Bhattacharyya Proceedings of the NCC, 2012 1-5 (2012)
  • Design of a low power, high speed complementary input folded regulated cascode OTA for a parallel pipeline ADC by Manas Kumar Hati and Tarun K. Bhattacharyya  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011 114-119 (2011)
  • Design of Low power Parallel Pipeline ADC in 180nm standard CMOS Process by Manas Kumar Hati and Tarun K. Bhattacharyya  International Conference on Communications and Signal Processing (ICCSP), 2011 9-13 (2011)
  • Implementation of Dynamic Element Matching DAC and its use for Noise Cancellation in Delta Sigma Fractional-N PLL by Manas Kumar Hati and Tarun K. Bhattacharyya IEEEE ICCPCT-2014 Six pages (2014)
  • A 10-b, 500 MSPS Current Steering CMOS DAC with a Switching Current Cell and High SFDR Value by Manas Kumar Hati and Tarun K. Bhattacharyya APCCAS 2014 (Japan) four pages (2014)
  • A PFD and Charge Pump Switching Circuit to Optimize the Output Phase Noise of the PLL in 0.13 um CMOS by Manas Kumar Hati and Tarun K. Bhattacharyya VLSI-SATA 1-6 (2015)
  • An 8-b 250-Msample/s Power Optimized Pipelined A/D Converter in 0.18 um CMOS by Manas Kumar Hati and Tarun K. Bhattacharyya VLSI-SATA 1-6 (2015)
  • Efficient Design Technique for Pulse Swallow Based Fractional-N frequency Divider by Manas Kumar Hati and Tarun K. Bhattacharyya ISCAS-2015 1-4 (2015)
  • Implementation of Digital Delta Sigma Modulator and a Divider Circuit for Fractional-N PLL by Manas Kumar Hati and Tarun K. Bhattacharyya IEEE Microcom 2016 1-6 (2016)

Indian Institute of Technology, Kharagpur-721 302, INDIA
Telephone Number +91-3222-255221 | FAX : +91-3222-255303