Doctorates' Information System

     Ashis Maity

Ph.D. fromIndian Institute of Technology-Kharagpur, India - Advanced Technology Developement Center
Supervisor(s)  Prof. Amit Patra
Ph.D. status  Joined in 2009 :: In progress
AddressS/O-Gostha Behari Maity, Vill-Bargachia, PO-Mecheda, Dist.-Midnapore(E), Pin-721137
Phone+91-9434192950
Emailashis.iit@gmail.com
Formal Education
Exam / Degree Board / UnivBranchYear
M.Tech.Indian Institute of Technology, KharagpurElectrical Engineering2009
BEBengal Enginnering and Science University, ShibpurElectronics and Telecommunication2002
12West Bengal Council of Higher Secondary Education / K.T.P.P. High SchoolScience1997
10West Bengal Board of Secondary Education / Boghpur K.M. High SchoolNA1995

Research Areas
  • High Performace Power Management Circuits for Portable and Low Power Applications.

Skills
  • Analog and Mixed-Signal Design and Layout in Cadence Environment
  • Accustomed with Full-Chip Design Flow
  • HDL- Verilog, VHDL
  • Scripting Language- OCEAN, PEARL
  • Operating Systems- UNIX, LINUX, WINDOWS

Awards
  • Winner as Best Entry in PhD Forum in 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems (2016)
  • Project guide and co-recipient of the runners up award in Cadence Design Contest-India (2012)
  • Second Prize Winner in the Poster Presentation in the Departmental Research Scholar Day (2012)
  • Project guide and co-recipient of the first place award in Cadence Design Contest-India (2011)
  • One of the finalist in Cadence Design Contest-India (2008)

Experience
  • June, 2008 to June, 2009 as Senior Design Engineer, National Semiconductor, Tokyo, Japan.
  • October, 2007 to November, 2007, Internship in National Semiconductor, Tokyo, Japan
  • May, 2007 to July, 2007, Internship in National Semiconductor, Tokyo, Japan
  • January, 2006 - May, 2008 as Research Consultant, Advanced VLSI Design Lab., Indian Institute of Technology-Kharagpur
  • July, 2002 to December, 2005 as Member Design Team, Alliance Semiconductor (India) Private Limited, Bangalore, India

Teaching Experience
  • MIXED SIGNAL CIRCUITS AND SYSTEMS ON CHIP(P) at IIT Kharagpur 6 months (1 terms)

Fellowships / Scholarships
  • Fellowship from 2009 to till date approved by Ministry of Human Resource Development (MHRD), Govt. of India

Papers Published in Journals
  • A Hybrid Mode Operational Trans-conductance Amplifier for an Adaptively Biased Low Dropout Regulator by Ashis Maity and Amit Patra IEEE Transactions on Power Electronics DOI 10.1109/TPEL.2016.2554400 (2016)
  • Analysis, Design and Performance Evaluation of a Dynamically Slew Enhanced Adaptively Biased Capacitor-less Low Dropout Regulator by Ashis Maity and Amit Patra IEEE Transactions on Power Electronics vol. 31, no. 10, pp. 7016-7028 (2016)
  • A Single Stage Low Dropout Regulator With a Wide Dynamic Range for Generic Applications by Ashis Maity and Amit Patra IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol. 24, no. 6, pp. 2117-2127 (2016)
  • Design and Analysis of an Adaptively Biased Low Drop-out Regulator Using Enhanced Current Mirror Buffer by Ashis Maity, and Amit Patra IEEE Transactions on Power Electronics vol.31, no.3, pp.2324-2336, March (2016)
  • Trade-offs Aware Design Procedure for an Adaptively Biased, Capacitor-less Low Drop-out Regulator Using Nested Miller Compensation by Ashis Maity, and Amit Patra IEEE Transactions on Power Electronics vol.31, no.1, pp.369-380, Jan. (2016)
  • Dynamic Slew Enhancement Technique for Improving Transient Response in an Adaptively Biased Low-Dropout Regulator by Ashis Maity, and Amit Patra IEEE Transactions on Circuits and Systems-II, Express Briefs Vol.62, no.7, pp.626-630, July (2015)
  • High Gain, Wide Band Error Amplifier Topology for DC-DC Buck Converter Switching at 20MHz by Ashis Maity, Norihisa Yamamura, Jonathan Knight, Amit Patra Electronics Letters Vol. 44, No. 11, Pages 655-656 (2008)
  • Design of a low power voltage regulator for high dynamic range of load current by Ashis Maity, R. G. Raghavendra, Pradip Mandal International Journal of Electronics Volume 94, Issue 8, pages 743 - 757 (2007)
  • Dynamically Biased Amplifier Circuit and Methods for Improving its Dynamic Range by Ashis Maity, and Amit Patra Indian Patent Application 564/KOL/2013 (2013)
  • An Adaptively Biased Self-compensated, Unconditionally Stable, Area Efficient LDO Topology by Ashis Maity, Amit Patra Indian Patent Application 111/KOL/2012 (2012)
  • A Bi-Directional Multiple-Input Single-Inductor Multiple-Output Switcher with Buck/Boost/Inverted Outputs by Amit Patra, Pradipta Patra, Syed Asif Eqbal, Ashis Maity Indian Patent Application 1328/KOL/2010 (2010)

Papers Presented at Conferences
  • Light Load Efficiency Improvement in High Frequency DC-DC Buck Converter Using Dynamic Width Segmentation of Power MOSFET by Metilda Sagaya Mary N.J, Ashis Maity and Amit Patra VLSI Design and 2013 13th International Conference on Embedded Systems (VLSID), 2014 27th International Conference on vol., no., pp.563,568, 5-9 Jan. (2014)
  • A Capacitor-less Low Drop-out (LDO) Regulator with Improved Transient Response for System-on- Chip Applications by Cheekala Lovaraju, Ashis Maity and Amit Patra VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on vol., no., pp.130,135 (2013)
  • Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications by Debajit Bhattacharya, Ashis Maity and Amit Patra VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on vol., no., pp.209-214 (2013)
  • Design of an Ultra-Low Powered DC-DC Buck Converter for Wireless Sensor Networks by Soumik Sarkar, Ashis Maity and Amit Patra Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in vol., no., pp.126-131 (2012)
  • Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications by Ashis Maity, Amit Patra, Norihisa Yamamura, Jonathan Knight 24th International Conference on VLSI Design held jointly with 10th International Conference on Embedded Systems Design, 2011 Vol. Page (2011)
  • On-chip Voltage Regulator with Improved Transient Response by Ashis Maity, R. G. Raghavendra, Pradip Mandal 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005 Vol. Pages 522 - 527 (2005)

Indian Institute of Technology, Kharagpur-721 302, INDIA
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