Doctorates' Information System

     Chandan Karfa

Ph.D. fromIndian Institute of Technology Kharagpur - Department of Computer Science and Engineering
Supervisor(s)  Prof. C. Mandal and Prof. D. Sarkar
Ph.D. status  Joined in 2008 :: In progress
AddressDepartment of Computer Science and Engineering, IIT Kharagpur, WB, 721302
Phone9433244530
Emailchandan.karfa@gmail.com
Formal Education
Exam / Degree Board / UnivBranchYear
M.Sc.Indian Institute of Technology KharagpurComputer Science2007
B.Tech.University of Kalyani, Nadia, West bengalInformation Technology2004
12West Bangal Council of Higher Secondrary EducationScience2000
10West bengal Board of Secondrary EducationMadhyamik1998

Research Areas
  • Formal Verification
  • Embedded Systems
  • High-level Synthesis

Skills
  • Languages-- C, CPP, Verilog

Awards
  • Innovative Student Projects Award (Master Level) from Indian National Academy of Engineering (INAE) in 2008,
  • Best Student Paper Award in ADCOM conference in 2007
  • Microsoft Research India PhD fellowship from Microsoft Research India in 2008
  • Third prize in PhD poster contest in TechVista 2010 organized by Microsoft Research India
  • First prize in EDA contest in 22nd International Conference on VLSI Design 2009
  • Winner in the Eastern Region and Runner up in the National Level the Young IT Professional Award 2007 contest organized by Computer Society of India

Experience
  • JPA in the project High-level synthesis and verification of digital circuits sponsored by MHRD under SRIC, IIT Kharagpur from July 2004-March 2007
  • Research Conslutant in Advanced VLSI Design Lab, IIT Kharagpur from April 2007-June 2008

Teaching Experience
  • Formal Systems(T) at Department of Computer Science and Engineering, IIT Kharagpur Spring 2009, Spring 2010 (2 terms)
  • Logic for Computer Science(T) at Department of Computer Science and Engineering, IIT Kharagpur Autumn 2009 (1 terms)
  • Programming and Data Structure Lab(P) at Department of Computer Science and Engineering, IIT Kharagpur Spring 2005, Spring 2006, (2 terms)
  • Operating Systems Lab(P) at Department of Computer Science and Engineering, IIT Kharagpur Autumn 2005 (1 terms)
  • Computing Systems Lab(P) at Department of Computer Science and Engineering, IIT Kharagpur Autumn 2007 (1 terms)
  • Programming and Data Structure Theory(T) at Department of Computer Science and Engineering, IIT Kharagpur Autumn 2008 (1 terms)

Fellowships / Scholarships
  • Microsoft Research India PhD Fellowship from Microsoft Research India for the period of August 2008 - July 2012

Papers Published in Journals
  • Verification of Datapath and Controller Generation Phase in High-level Synthesis of Digital Circuits by Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal IEEE Transaction on Computer Aided Design on Intregrated Circuits and Systems Vol. 29, No 3, pages 472--492 (2010)
  • Verification and Synthesis of Digital Circuits -- High-level Synthesis and Equivalence Checking (BOOK) by Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal LAP LAMBERT Academic Publishing 978-3-8383-9813-6 (isbn) (2010)
  • An Equivalence Checking Method for Scheduling Verification in High-level Synthesis by Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal and Pramod Kumar IEEE Transaction on Computer Aided Design on Intregrated Circuits and Systems page 556-569, Vol 27, No. 3 (2008)

Papers Presented at Conferences
  • Verification of Register Transfer Level Low Power Transformations by Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011) (Accepted) (2011)
  • Equivalence Checking of Array-Intensive Programs by Chandan Karfa, Kunal Banerjee, Dipankar Sarkar and Chittaranjan Mandal IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011) (Accepted) (2011)
  • Data-flow Driven Equivalence Checking for Verification of Code Motion Techniques by Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010) 428-433 (2010)
  • Verification of Data-path and Controller Generation Phase in High-level Synthesis by Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal 15th IEEE International Conference on Advanced Computing and Communication (ADCOM 2007) page 315-320 (2007)
  • Hand-in-hand Verification of High-level Synthesis by Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal 17th ACM Great Lakes Symposium on VLSI 2007 (GLSVLSI 2007) page 429-434 (2007)
  • Register Sharing Verification during Data-path Synthesis by Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal and Chris Reade International Conference on Computing- Theory and Application 2007 (ICCTA 2007) page 135-140 (2007)
  • A Formal Verification Method of Scheduling in High-level Synthesis by Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Satyam R Pentakota and Chris Reade  7th IEEE International Symposium on Quality Electronic Design (ISQED 2006) page 71-76 (2006)
  • Fairness of Transitions in Diagnosability Analysis of Hybrid Systems by S. Biswas, Chandan Karfa, H. Kanwar, D. Sarkar, S. Mukhopadhyay A. Patra American Control Conference (ACC 2006) page 2664-2669 (2006)
  • Verification of Scheduling in High-level Synthesis by Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Satyam R Pentakota and Chris Reade IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006) Page 141-146 (2006)
  • SAST- An Interconnection aware high level synthesis tool by Chandan Karfa, Jala Srinivas Reddy, Santosh Biswas, Dipankar Sarkar and Chittaranjan Mandal 9th VLSI Design and Test (VDAT 2005) page 285-293 (2005)

Indian Institute of Technology, Kharagpur-721 302, INDIA
Telephone Number +91-3222-255221 | FAX : +91-3222-255303